Charge redistribution converters include capacitors which are charged in a first sampling step. Then in a second digitization step, the electrical charges are transferred from one capacitor to another. The second digitization step is therefore a charge redistribution step.
The disclosure applies advantageously but not restrictively to image acquisition chains.
A digital camera includes an image acquisition chain notably including a pixel matrix e.g. of dimension n×m having n pixels aligned on the same line, and m lines being superimposed on each other, m and n being non-zero whole numbers.
FIG. 1 represents an example of an image acquisition chain of a pixel CH according to the prior art. Each pixel incorporated in the pixel matrix of dimension n×m is included in an image acquisition chain, in other words there are as many acquisition chains as columns in the pixel matrix, e.g. here there are m acquisition chains.
The chain CH includes a pixel 1 and a charge redistribution analog-to-digital converter 2.
An output S1 of the pixel 1 is connected to an input E2 of the converter 2.
The pixel 1 includes a photodiode, switching transistors and bias transistors. The photodiode generates at its output S1 two successive signals, the difference of which is proportional to the captured light intensity.
The two signals are successively converted by the device 2 into two distinct digital words.
In what follows, only the processing of a first analog signal s1 emitted by the pixel 1 is described in detail, the processing of a second signal emitted by the pixel 1 by the device 2 being identical to the processing of the first signal s1.
The analog signal s1 is converted by the device 2 into a digital word s2.
FIG. 2 represents an example of a charge redistribution analog-to-digital converter 2 of the 4-bit type according to the prior art.
The converter 2 includes a sampler 4, a four-bit type charge redistribution analog-to-digital conversion device 5, a comparator COMP and a state machine 3.
The sampler 4 includes an input E4 connected to the input E2, an output S4 connected to an input E5 of the device 5 and a control input Ec4 connected to an output S3 of the state machine 3.
The device 5 includes three connection terminals connected to three reference potential sources of different values of value Vref1, Vref2 and Vref3 connected to the connection terminals E5REF1, E5REF2 and E5REF3, respectively, and an output S5 connected to a non-inverting input ECOMP1 of the comparator COMP.
The device 5 further includes four control inputs E51, E52, E53 and E54, connected to four outputs S31, S32, S33 and S34 respectively of the state machine 3.
The comparator COMP further includes an inverting input ECOMP2 connected here to the potential source Vref4 and an output S connected to an input E3 of the state machine 3.
The state machine 3 includes an input ECLK connected to a clock CLK and four outputs S3a, S3b, S3c and S3d connected to the output interface S2. Each output S3a, S3b, S3c and S3d delivers a bit a, b, c and d, respectively.
The state machine 3 further includes a programmable processing unit UT. The programmable processing unit UT may be implemented by a processor (e.g. a microprocessor) known in the art.
FIG. 3 represents an example of a four-bit type device 5 according to the prior art.
The device 5 includes a line L connecting the input E5 to the output S5 and five capacitors C1, C2, C3, C4 and C5.
The capacitor C5 has a capacitance C0. The capacitors C1, C2, C3 and C4 have, for example, capacitances equal to 8 times C0, 4 times C0, 2 times C0 and C0 respectively.
A first terminal E1C1, E1C2, E1C3, E1C4 and E1C5 of each of the capacitors C1, C2, C3, C4 and C5 respectively is connected to the line L.
A second terminal E2C1, E2C2, E2C3 and E2C4 of each of the capacitors C1, C2, C3 and C4, respectively, is connected to an input EMC1, EMC2, EMC3, EMC4, respectively, of switching circuits referenced MC1, MC2, MC3 and MC4 respectively.
A second terminal E2C5 of the capacitor C5 is connected to the input E5REF3.
The switching circuits MC1, MC2, MC3 and MC4 each includes a control input EE51, EE52, EE53 and EE54 respectively connected to the input E51, E52, E53 and E54, respectively.
The switching circuits MC1, MC2, MC3 and MC4 respectively include: an input E1REF1, E2REF1, E3REF1 and E4REF1 respectively connected to the input E5REF1; an input E1REF2, E2REF2, E3REF2 and E4REF2 respectively connected to the input E5REF2; and an input E1REF3, E2REF3, E3REF3 and E4REF3 respectively connected to the input E5REF3.
The switching circuits MC1, MC2, MC3 and MC4 are configured for connecting the input EMC1, EMC2, EMC3, EMC4 respectively to one of the inputs E5REF1, E5REF2 or E5REF3 according to the control signal applied to the control input.
The programmable processing unit UT is configured for driving the sampler 4. The state machine 3 drives the switching circuits MC1, MC2, MC3 and MC4 according to the signal SCOMP delivered at the output S of the comparator COMP and according to the clock signal SCLK received at the input ECLK.
The programmable processing unit UT is further configured for transmitting a four-bit digital word to the output interface S2.
The potentials Vref1 and Vref2 are, for example, of the same value equal to the maximum value of the signal s1 and of opposite signs, and the potential Vref3 is connected to an earth. In this case the potential Vref4 is connected to the earth.
In operation, a signal s1 is generated, for example, by the pixel 1 and is transmitted to the input E2.
FIG. 4 depicts an example of signals s1 and sp according to time.
The signal s1 includes the noise generated notably by the switching of the transistors incorporated in the pixel.
The signal sp of amplitude Ap is a representation of the signal s1 not including any noise.
The sampler 4 operates at a sampling frequency Fe of period Te.
In a first step, the sampler 4 records a value A1 of the signal s1 at an instant t1. This voltage value is transmitted to the input E5 of the device 5.
The circuits MC1 to MC4 are driven so that the second terminal of capacitors C1 To C4 is coupled to the input E5REF3.
The capacitors C1 to C5 are now charged.
In a second step, the sampler 4 is “off”, i.e. no signal is transmitted to the input of the device 5.
In a third step, the device 5 implements a dichotomy algorithm known to the person skilled in the art.
A dichotomy is applied on the interval [−Vref; Vref] in which the value of the signal s1 recorded by the sampler 4 is situated.
At the end of this step, the processing unit UT determines the digital word corresponding to the value of the signal s1 recorded by the sampler 4 and delivers the four-bit digital word.
The digital word is transmitted to the output interface S2 including four outputs a, b, c and d.
The output a corresponds to the bit known to the person skilled in the art as the “Most Significant Bit” MSB and the output d corresponds here to the bit known to the person skilled in the art as the “Least Significant Bit” LSB.
However, the signal s1 at instant t1 has an amplitude A1 different from the amplitude Ap of the signal sp, i.e. of the non-noisy signal emitted by the pixel 1.
The resolution of the device 5 is such that the amplitude A1 is included in a quantum interval [C2; C3] corresponding here to the binary word 0110 while the amplitude Ap is included in a quantum interval [C3; C4] corresponding here to the digital word 0111.
Then the preceding steps are repeated at instant t2 corresponding to the duration t1 plus Te. The amplitude at instant t2 of the signal s1 is equal to A2. It is noted that at this instant the digital word generated by the device 5 is 1000.
At each sampling instant, a single value of the signal s1 is recorded. As the signal s1 fluctuates randomly, the digital value representing the color associated with the pixel 1s dependent on the noise.
In the reproduction of the image, the quality of the latter will be degraded.
One solution consists in modifying the resolution of the device 5 so that the device 5 is insensitive to noise by expanding the intervals [C2; C3] and [C3; C4]. However, the resolution of the device 5 is degraded, and consequently the definition of the reproduced image is coarse.
There is a need for a charge redistribution analog-to-digital converter less sensitive to the noise borne by the analog signal to be converted, the architecture of which is similar to a charge redistribution analog-to-digital converter known to the prior art.